1. Field of the Invention
The present invention relates generally to an analog-to-digital converter. More particularly, this invention relates to an analog-to-digital converter for converting an analog composite video signal into a digital composite video signal.
2. Background of the Invention
FIG. 1 shows a conventional analog-to-digital converter (hereinafter referred to simply as "A/D converter") for converting an analog composite video signal (hereinafter referred to simply as "analog composite signal") into a digital composite video signal (hereinafter referred to simply as "digital composite signal"). This circuit includes an amplifier 31 for amplifying an analog composite signal, a clock generating circuit 32 for generating a sampling clock with a frequency 4 f.sub.sc indicating that in this example the frequency is four times that of a subcarrier wave (hereinafter referred to simply as "subcarrier") superimposed as a color burst signal on the analog composite signal. This analog composite signal is amplified by the amplifier 31, and an A/D conversion circuit 33 converts the analog composite signal into a digital composite signal on the basis of the sampling clock generated by the clock generating circuit 32. The clock signal generated by clock generator 32 is fed forward to clock the A/D converter 33 in this circuit configuration.
The clock generator 32 of FIGURE i includes a band pass filter (BPF) 36 for filtering the output of the amplifier 31. This output is the amplified analog composite video signal which is to be converted to a digital composite signal. The BPF 36 output drives a burst gate 38 which in turn drives one input of a phase detector 40. The output of the phase detector 40 is processed by a pulse-width-to-voltage converter 44 (generally a low pass filter). The output voltage from pulse-width-to-voltage converter 44 is used to control the output frequency of a voltage controlled oscillator (VCO) 46, the output of which forms the output of the clock generator 32.
In the example shown, the VCO 46 operates at four times the sampling clock frequency f.sub.sc. This output is also provided to a frequency divider 50 which in the example divides the output of the VCO by four and supplies the divided signal to a second input of the phase detector 40. The phase detector 40 compares the phase of the two inputs to obtain the error signal to converter 44. Those skilled in the art will recognize the structure of elements 40, 44, 46 and 50 as a frequency multiplying phase-locked-loop (PLL). The analog-to-digital converter 33 processes the analog composite video signal from amplifier 31 to produce the desired digital composite signal.
In one embodiment of the present invention, the digital composite signal output conforms to relevant standards, for instance, so-called D - 2 Format as defined by the National Television System Committee (NTSC).
D - 2 Format is stipulated in standards 244 M to 248 M formulated by the American National Standard Institute (ANSI) and the Society of Motion Picture and Television Engineers (SMPTE) which are hereby incorporated by reference. As the main coding parameters of D - 2 Format, the sampling frequency is 4 f.sub.sc, the quantization type is linear 8-bit (10-bit for a color burst signal portion) quantization, and the sampling phase is an IQ axis for precise restriction of a color signal (hereinafter referred to as "IQ signal").
Accordingly, the PLL of the clock generating circuit 32 is designed to generate a sampling clock on the basis of a subcarrier superimposed as a color burst signal on the analog composite signal amplified by the amplifier 31. The sampling clock thus generated has a frequency of 4 f.sub.sc and a phase of 123 degrees relative to the subcarrier. To ensure these settings of the sampling clock, the clock generating circuit 32 is pre-adjusted before shipment, for instance, during manufacture.
Even though the clock generating circuit 32 is pre-adjusted during manufacture as mentioned above, the phase setting of the sampling clock may vary for such causes as changes with time in temperature characteristics of electrical elements of the PLL and fluctuations in supply voltage. As a result, the digital composite signal output by the A/D converter may fail to conform to relevant standards. Further, such pre-adjustment requires additional processes during manufacture. These problems are addressed with the present invention.